1. Field of the Invention
The invention relates generally to complementary metal oxide semiconductor (CMOS) structures. More particularly, the invention relates to CMOS structures with enhanced performance.
2. Description of the Related Art
As semiconductor technology has advanced, and semiconductor structure and semiconductor device dimensions have decreased to a point that may be challenging physical limitations of semiconductor fabrication apparatus, alternative novel approaches have evolved for fabricating semiconductor structures and semiconductor devices with continued enhanced performance. One such alternative novel approach is predicated upon the observation that a charge carrier mobility of a field effect device may be optimized in connection with a selection of a particular crystallographic orientation, and a particular strain, of a semiconductor substrate within and upon which is fabricated the field effect device.
To that end, the use of hybrid orientation technology (HOT) substrates has become more common in the semiconductor fabrication art. A hybrid orientation technology substrate includes multiple semiconductor regions of different crystallographic orientation, and typically also dopant polarity, supported upon a single substrate.
Particular crystallographic orientation specific and strain specific effects upon charge carrier mobility within semiconductor structures are known in the semiconductor fabrication art.
Particular disclosures include: (1) Irie et al., “In-Plane Mobility Anisotropy and Universality Under Uni-axial Strains in n- and p-MOS Inversion Layers on (100), (110) and (111) Si,” IEDM Technical Digest, December 2004, pp. 225-228; and (2) Mizuno et al., in “(110)-Surface Strained-SOI CMOS Devices,” IEEE Trans on Electron Devices, 52(3), March 2005, pp. 367-374.
Various aspects of hybrid orientation technology substrates, including CMOS structure fabrication using hybrid orientation technology substrates, are also known in the semiconductor fabrication art.
Particular disclosures include: (1) Ieong et al., U.S. Pat. No. 6,815,278, U.S. Pat. No. 7,023,055 and U.S. Pub. No. 2006/0194421 (CMOS structures using hybrid orientation substrates and also including direct semiconductor substrate bonding); (2) Doris et al., U.S. Pub. No. 2004/0256700 (CMOS structures using hybrid orientation substrates and also including direct semiconductor substrate bonding); (3) Yeo et al., in U.S. Pat. No. 6,902,962 (CMOS structures using hybrid orientation substrates including silicon islands); (4) Chan et al., U.S. Pub. No. 2005/0236687 (CMOS structures using hybrid orientation substrates and also including direct semiconductor substrate bonding); (5) Wu et al. U.S. Pub. No. 2006/0292770 (CMOS structures using hybrid orientation substrates derived from double semiconductor-on-insulator (SOI) substrates); (6) Chuang et al., U.S. Pub. No. 2007/0018248 (a multiple threshold CMOS structure fabricated using an epitaxial semiconductor-on-insulator hybrid orientation substrate); and (7) Chan et al., U.S. Pub. No. 2007/0040235 (CMOS structures using hybrid orientation substrates and also including dual dimensioned isolation trenches).
Additional general and specific disclosures pertinent to hybrid orientation technology substrates include: (1) Yang et al., “Hybrid-Orientation Technology (HOT): Opportunities and Challenges,” IEEE Trans. on Electron Devices, 53(3), May 2006, pp. 965-78; (2) Yang et al., “High Performance CMOS Fabricated on Hybrid Substrate With Different Crystallographic Orientations,” IEDM Technical Digest, December 2003, pp. 18.7.1-18.7.4; and (3) Doris et al., “A Simplified Hybrid Orientation Technology (SHOT) for High Performance CMOS.” 2004 Symp. on VLSI Technology Digest of Technical Papers, IEEE 2004, pp. 86-87.
The use of hybrid orientation technology substrates is likely to continue to evolve in prominence as semiconductor technology advances. To that end desirable are hybrid orientation technology substrates and related semiconductor structures, and methods for fabrication thereof, that provide for enhanced performance of semiconductor devices that are included within the semiconductor structures.